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ASAHI KASEI
[AK5353]
96kHz 24Bit ADC with Single-ended Input
AK5353
GENERAL DESCRIPTION The AK5353 is a stereo A/D Converter with wide sampling rate of 4kHz96kHz and is suitable for multimedia audio system. The AK5353 achieves high accuracy and low cost by using Enhanced dual bit techniques. The AK5353 requires no external components because the analog inputs are singleended. The audio interface has two formats (MSB justified, I 2S) and can correspond to many systems like Karaoke, surround. FEATURES o Stereo ADC o On-Chip Digital Anti-Alias Filtering o Single-ended Input o Digital HPF for DC-Offset cancel o S/(N+D): 84dB@5V, 80dB@3V for 48kHz o DR: 96dB@5V, 92dB@3V for 48kHz o S/N: 96dB@5V, 92dB@3V for 48kHz o Sampling Rate Ranging from 4kHz to 96kHz o Master Clock: 256fs/384fs/512fs (48kHz) 256fs/384fs (96kHz) o Low Power Dissipation: 70mW o Small 16pin TSSOP Package o Power Supply: 2.75.5V (48kHz) 4.55.5V (96kHz) o Ta=-4085C o Input level: TTL/CMOS selectable o Output format: 24bit MSB justified / I2S selectable
VA AGND
VD DGND
MCLK
Clock Divider AINL Modulator Modulator Voltage Reference Decimation Filter Decimation Filter Serial I/O Interface
LRCK SCLK
AINR
SDTO
VCOM VREF
TST
PD
DIF
TTL
M0067-E-00 -1-
1999/06
ASAHI KASEI
[AK5353]
n Ordering Guide
AK5353VT AKD5353 -40+85C Evaluation Board 16pin TSSOP
n Pin Layout
AINR AINL VREF VCOM AGND VA VD DGND
1 2 3 4 5 6 7 8
16 15 14
TST TTL DIF PDN SCLK MCLK LRCK SDTO
Top View
13 12 11 10 9
M0067-E-00 -2-
1999/06
ASAHI KASEI
[AK5353]
PIN/FUNCTION
No. 1 2 3 Pin Name AINR AINL VREF I/O I I O Description Rch Analog Input Pin Lch Analog Input Pin Voltage Reference Output Pin Normally connected to AGND with a 0.1uF ceramic capacitor in parallel with an electrolytic capacitor less than 4.7uF. Common Voltage Output Pin Normally connected to AGND with a 0.1uF ceramic capacitor in parallel with an electrolytic capacitor less than 4.7uF. Analog Ground Pin, 0V Analog Power Supply Pin, +2.7+5.5V Digital Power Supply Pin, +2.7+5.5V Digital Ground Pin, 0V Serial Data Output Pin Data bits are presented MSB first, in 2 s complement format. This pin is L in the power-down mode. Left/Right Channel Select Pin The fs clock is input to this pin. Master Clock Input Pin Serial Data Input Pin Output data is clocked out on the falling edge of SCLK. Power-Down Pin When L , the circuit is in power-down mode. The AK5353 should always be reset upon power-up. Serial Interface Format Pin L : MSB justified, H : I2S Digital Input Level Select Pin L : CMOS level (VA,VD=2.75.5V), H : TTL level (VA,VD=4.55.5V) Test Pin (Internal pull-down pin) This pin should be left floating.
4
VCOM
O
5 6 7 8 9
AGND VA VD DGND SDTO
O
10 11 12 13
LRCK MCLK SCLK PDN
I I I I
14 15 16
DIF TTL TST
I I I
Note: All input pins except pull-down pins should not be left floating.
M0067-E-00 -3-
1999/06
ASAHI KASEI
[AK5353]
ABSOLUTE MAXIMUM RATINGS (AGND, DGND=0V; Note 1) Parameter Symbol min Power Supplies Analog (VA pin) VA -0.3 Digital (VD pin) VD -0.3 |AGND-DGND| GND Input Current (any pins except for supplies) IIN Analog Input Voltage (AINL, AINR pins) VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature Ta -40 Storage Temperature Tstg -65
Note:1. All voltages with respect to ground. 2. AGND and DGND must be connected to the same analog ground plane.
max 6.0 6.0 0.3 10 VA+0.3 VD+0.3 85 150
Units V V V mA V V C C
WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (fs=48kHz) (AGND, DGND=0V; Note 1) Parameter Symbol min typ Power Supplies Analog VA 2.7 5.0 (Note 3) Digital VD 2.7 5.0 Sampling Rate fs 4
Note:1. All voltages with respect to ground. 3. The power up sequence between VA and VD is not critical.
max 5.5 VA 48
Units V V kHz
RECOMMENDED OPERATING CONDITIONS (fs=96kHz) (AGND, DGND=0V; Note 1) Parameter Symbol min typ Power Supplies Analog VA 4.5 5.0 (Note 3) Digital VD 4.5 5.0 Sampling Rate fs 4
Note:1. All voltages with respect to ground. 3. The power up sequence between VA and VD is not critical.
max 5.5 VA 96
Units V V kHz
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
M0067-E-00 -4-
1999/06
ASAHI KASEI
[AK5353]
ANALOG CHARACTERISTICS (Ta=25C; VA,VD=5V; fs=48kHz; I/F format=Mode 0; Signal Frequency =1kHz; Measurement band width=20Hz20kHz; unless otherwise specified) Parameter min typ max ADC Analog Input Characteristics: Analog source impedance=470 (BW=40Hz40kHz at fs=96kHz) Resolution 24 S/(N+D) (-1dBFS) (Note 4) fs=48kHz, VA=5V 76 84 fs=48kHz, VA=3V 76 84 fs=96kHz, VA=5V 84 DR (-60dBFS) (Note 5) fs=48kHz, VA=5V, A-weighted 90 96 fs=48kHz, VA=3V, A-weighted 86 92 fs=96kHz, VA=5V 93 S/N fs=48kHz, VA=5V, A-weighted 90 96 fs=48kHz, VA=3V, A-weighted 86 92 fs=96kHz, VA=5V 93 Interchannel Isolation 78 90 DC Accuracy Interchannel Gain Mismatch 0.1 0.3 Gain Drift 100 150 Input Voltage (Note 6) 2.7 3.0 3.3 Input Resistance (Note 7) 40 60 Power Supply Rejection (Note 8) 30 Power Supplies Power Supply Current Normal Operation (PDN= H ) VA+VD (Note 9) 14 21 Power-Down Mode (PDN= L ) VA+VD 10 100
Units Bits dB dB dB dB dB dB dB dB dB dB dB ppm/C Vpp k dB
mA A
Note:4. The ratio of the rms value of the signal to the rms sum of all the spectral components less than 20kHz bandwidth, including distortion components. 5. S/(N+D) which is measured with an input signal of -60dB below full-scale. 6. This value is the full scale(0dB) of the input voltage. Input voltage is proportional to VA. (Vin=0.6xVA) 7. 40k(typ) and 25k(min) at fs=96kHz. 8. PSR is applied to VA,VD with 1kHz, 50mVpp. 9. VA=11mA; VD=3mA@48kHz,5V, 1.5mA@48kHz,3V, 6mA@96kHz,5V (typ).
M0067-E-00 -5-
1999/06
ASAHI KASEI
[AK5353]
FILTER CHARACTERISTICS (fs=48kHz) (Ta=25C; VA,VD=2.75.5V; fs=48kHz) Parameter Symbol min typ Digital Filter (Decimation LPF) Passband (Note 10) PB 0 0.1dB 20.0 -0.2dB 21.8 -1.0dB 23.0 -3.0dB Stopband (Note 10) SB 29.4 Stopband Attenuation SA 65 Group Delay Distortion 0 GD Group Delay (Note 11) GD 17.0 Digital Filter (HPF) Frequency Response: -3 dB FR 4 -0.5dB 11 -0.1dB 24
max 18.9 -
Units kHz kHz kHz kHz kHz dB s 1/fs Hz Hz Hz
-
Note:10. The passband and stopband frequencies scale with fs. 11. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 24bit data of both channels to the output register for ADC.
FILTER CHARACTERISTICS (fs=96kHz) (Ta=25C; VA,VD=4.55.5V; fs=96kHz) Parameter Symbol min typ Digital Filter (Decimation LPF) Passband (Note 10) PB 0 0.1dB 40.0 -0.2dB 43.6 -1.0dB 46.0 -3.0dB Stopband (Note 10) SB 58.8 Stopband Attenuation SA 65 Group Delay Distortion 0 GD Group Delay (Note 11) GD 17.0 Digital Filter (HPF) Frequency Response: -3 dB FR 8 -0.5dB 22 -0.1dB 48
max 37.8 -
Units kHz kHz kHz kHz kHz dB s 1/fs Hz Hz Hz
-
Note:10. The passband and stopband frequencies scale with fs. 11. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 24bit data of both channels to the output register for ADC.
M0067-E-00 -6-
1999/06
ASAHI KASEI
[AK5353]
DIGITAL CHARACTERISTICS (CMOS level input) (Ta=25C; VA,VD=2.75.5V; TTL= L ) Parameter Symbol min typ High-Level input voltage VIH 0.7xVD Low-Level input voltage VIL VOH VD-0.5 High-Level output voltage (Iout= -100A) VOL Low-Level output voltage (Iout= 100A) Input leakage current (exclude TST pin) Iin -
Max 0.3xVD 0.5 10
Units V V V V A
DIGITAL CHARACTERISTICS (TTL level input; except for TTL pin) (Ta=25C; VA,VD=4.55.5V; TTL= H ) Parameter Symbol min typ Max High-Level input voltage (TTL pin) VIH 0.7xVD (All pins except for TTL pin) VIH 2.2 Low-Level input voltage (TTL pin) VIL 0.3xVD (All pins except for TTL pin) VIL 0.8 VOH VD-0.5 High-Level output voltage (Iout= -100A) VOL 0.5 Low-Level output voltage (Iout= 100A) Input leakage current (exclude TST pin) Iin 10
Units V V V V V V A
M0067-E-00 -7-
1999/06
ASAHI KASEI
[AK5353]
SWITCHING CHARACTERISTICS (VA,VD=4.55.5V) (Ta=25C; VA,VD=4.55.5V; CL=20pF) Parameter Symbol min typ Control Clock Frequency Master Clock 256fs: fCLK 1.024 12.288 Pulse Width Low tCLKL 16 Pulse Width High tCLKH 16 384fs: fCLK 1.536 18.432 Pulse Width Low fCLKL 10 Pulse Width High fCLKH 10 512fs: fCLK 2.048 24.576 Pulse Width Low fCLKL 16 Pulse Width High fCLKH 16 SCLK Frequency fSLK LRCK Frequency fs 48 4 Serial Interface Timing (Note 12) tSLK 160 SCLK Period tSLKL 65 SCLK Pulse Width Low tSLKH 65 Pulse Width High tLRSH 30 LRCK Edge to SCLK (Note 13) tSHLR 30 SCLK to LRCK Edge (Note 13) tDLR LRCK Edge to SDTO Valid (Note 14) tDSS SCLK to SDTO Valid Power-Down & Reset Timing PDN Pulse Width tPDW 150 tPDV 4129 PDN to SDTO delay (Note 15)
Note:12. Refer to the operating overview section Serial Data Interface . 13. SCLK rising edge must not occur at the same time as LRCK edge. 14. In case of MSB justified format. 15. These cycles are the number of LRCK rising from PDN falling.
max 24.576
Units MHz ns ns MHz ns ns MHz ns ns MHz kHz ns ns ns ns ns ns ns ns 1/fs
36.864
24.576
6.144 96
50 50
M0067-E-00 -8-
1999/06
ASAHI KASEI
[AK5353]
SWITCHING CHARACTERISTICS (VA,VD=2.74.5V) (Ta=25C; VA,VD=2.74.5V; CL=20pF) Parameter Symbol min typ Control Clock Frequency Master Clock 256fs: fCLK 1.024 Pulse Width Low tCLKL 32 Pulse Width High tCLKH 32 384fs: fCLK 1.536 Pulse Width Low fCLKL 21 Pulse Width High fCLKH 21 512fs: fCLK 2.048 Pulse Width Low fCLKL 16 Pulse Width High fCLKH 16 SCLK Frequency fSLK LRCK Frequency fs 4 Serial Interface Timing (Note 12) tSLK 160 SCLK Period tSLKL 65 SCLK Pulse Width Low tSLKH 65 Pulse Width High tLRSH 30 LRCK Edge to SCLK (Note 13) tSHLR 30 SCLK to LRCK Edge (Note 13) tDLR LRCK Edge to SDTO Valid (Note 14) tDSS SCLK to SDTO Valid Power-Down & Reset Timing PDN Pulse Width tPDW 150 tPDV 4129 PDN to SDTO delay (Note 15)
Note:12. Refer to the operating overview section Serial Data Interface . 13. SCLK rising edge must not occur at the same time as LRCK edge. 14. In case of MSB justified format. 15. These cycles are the number of LRCK rising from PDN falling.
max 12.288
Units MHz ns ns MHz ns ns MHz ns ns MHz kHz ns ns ns ns ns ns ns ns 1/fs
18.432
24.576
6.144 48
50 50
M0067-E-00 -9-
1999/06
ASAHI KASEI
[AK5353]
n Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fs
VIH
LRCK
VIL tSLK
VIH
SCLK tSLKH tSLKL
VIL
Clock Timing
LRCK
VIH VIL tSHLR tLRSH VIH VIL tDLR tDSS
SCLK
SDTO
50%VD
Serial Interface Timing
tPDW VIH VIL tPWV
PDN
SDTO
50%VD
Power-down & Reset Timing
M0067-E-00 - 10 -
1999/06
ASAHI KASEI
[AK5353]
OPERATION OVERVIEW n System Clock Input
The external clocks which are required to operate the AK5353 are MCLK(256fs/384fs/512fs), LRCK(1fs), SCLK. MCLK should be synchronized with LRCK but the phase is not critical. When 384fs or 512fs clock is input to MCLK pin, the internal master clock becomes 256fs(=384fs*2/3=512fs*1/2). Table 1 illustrates standard audio word rates and corresponding frequencies used in the AK5353. All external clocks (MCLK,BICK,LRCK) should always be present whenever the AK5353 is in normal operation mode (PDN= H ). If these clocks are not provided, the AK5353 may draw excess current and may not possibly operate properly because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK5353 should be in the power-down mode (PDN= L ). After exiting reset at power-up etc., the AK5353 is in the power-down mode until MCLK and LRCK are input. fs 32.0kHz 44.1kHz 48.0kHz 96.0kHz 256fs 8.1920MHz 11.2896MHz 12.2880MHz 24.5760MHz MCLK 384fs 12.2880MHz 16.9344MHz 18.4320MHz 36.8640MHz SCLK 64fs 2.0480MHz 2.8224MHz 3.0720MHz 6.1440MHz
512fs 16.3840MHz 22.5792MHz 24.5760MHz N/A
32fs 1.0240MHz 1.4112MHz 1.5360MHz 3.0720MHz
128fs 4.0960MHz 5.6448MHz 6.1440MHz N/A
Table 1. Example of System Clock
n Serial Data Interface
2 kinds of data format can be selected by DIF pin. The data is clocked out via the SDTO pin by SCLK corresponding to the setting of DIF pin. The format of output data is 2 s complement MSB first. Mode 0 1 DIF 0 1 Format 24bit, MSB justified, L/R, SCLK 48fs (16bit, MSB justified, L/R, SCLK 32fs) 24bit, I2S, SCLK 48fs (16bit, I2S, SCLK 32fs) Table 2. Audio Serial Interface Formats
M0067-E-00 - 11 -
1999/06
ASAHI KASEI
[AK5353]
LRCK
0 1 2 22 23 24 25 31 0 1 2 22 23 24 25 31 0 1
SCLK SDTO
23 22 21 23:MSB, 0:LSB 1 0 23 22 21 23:MSB, 0:LSB 1 0 23 22
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0 1 2 22 23 24 25 31 0 1 2 22 23 24 25 31 0 1
SCLK SDTO
23 22 2 1 0 23 22 2 1 0 23
23:MSB, 0:LSB
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1 Timing
M0067-E-00 - 12 -
1999/06
ASAHI KASEI
[AK5353]
n Power down
The AK5353 is placed in the power-down mode by bringing PDN L and the digital filter is also reset at the same time. This reset should always be done after power-up. In the power-down mode, the VREF and VCOM are AGND level. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after 4129 cycles of LRCK clock. During initialization, the ADC digital data outputs of both channels are forced to a 2 s complement 0 . The ADC outputs settle in the data corresponding to the input signals after the end of initialization (Settling approximately takes the group delay time).
4129/fs(86.021ms@fs=48kHz)
PDN Internal State A/D In (Analog) A/D Out (Digital) Clock In
MCLK,LRCK,SCLK
Normal Operation GD (1)
Power-down
Initialize
Normal Operation GD
Idle Noise
(2) 0 data
0 data
Idle Noise
(3)
Notes: (1) Digital output corresponding to analog input has the group delay (GD). (2) A/D output is 0 data at the power-down state. (3) When the external clocks (MCLK,SCLK,LRCK) are stopped, the AK5353 should be in the power-down state. Figure 3. Power-down/up sequence example
n System Reset
The AK5353 should be reset once by bringing PDN L after power-up. The internal timing starts clocking by the rising edge (falling edge at mode1) of LRCK upon exiting from reset.
M0067-E-00 - 13 -
1999/06
ASAHI KASEI
[AK5353]
SYSTEM DESIGN
Figure 4 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
4.7u
470 2.2n
Rch In
+
4.7u
470 2.2n 4.7u 0.1u + 0.1u
Lch In
+
1 2 3
AINR AINL VREF VCOM AGND Top View VA VD DGND
TST 16 TTL 15
Mode Control Power-down Control
AK5353
DIF 14 PDN 13 SCLK 12 MCLK 11 LRCK 10 SDTO 9
4.7u
0.1u +
4 5
Analog 5V
10u + 10u +
6 7
0.1u
Controller
8
Analog Ground
System Ground
Figure 4. Typical Connection Diagram Note: The value of electrolytic capacitor at VCOM depends on the low-frequency noise of power supply.
Digital Ground
Analog Ground
1
AINR AINL VREF VCOM AGND VA VD DGND
TST 16 TTL 15 DIF 14
System Controller
2 3 4 5 6 7 8
AK5353
PDN 13 SCLK 12 MCLK 11 LRCK 10 SDTO 9
Figure 5. Ground Layout Note: AGND and DGND must be connected to the same analog ground plane.
M0067-E-00 - 14 -
1999/06
ASAHI KASEI
[AK5353]
1. Grounding and Power Supply decoupling The AK5353 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is not critical. AGND and DGND of the AK5353 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5353 as possible, with the small value ceramic capacitor being the nearest. 2. On-chip voltage reference The voltage input to VA sets the analog input range. VREF and VCOM are 55%VA and normally connected to VA with a 0.1uF ceramic capacitor. An electrolytic capacitor 10uF parallel with a 0.1uF ceramic capacitor attached to VREF and VCOM pins eliminates the effects of high frequency noise. No load current may be drawn from these pins. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the AK5353. 3. Analog Inputs The ADC inputs are single-ended and internally biased to the common voltage (55%VA) with 100k (typ) resistance. The input signal range scales with the supply voltage and nominally 0.6xVA Vpp. The ADC output data format is 2 s complement. The output code is 7FFFFFH(@24bit) for input above a positive full scale and 800000H(@24bit) for input below a negative full scale. The ideal code is 000000H(@24bit) with no input signal. The DC offset is removed by the internal HPF. The AK5353 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. A simple RC filter (fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs.
M0067-E-00 - 15 -
1999/06
ASAHI KASEI
[AK5353]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0 1.10max
16
9 A 6.40.2 0.170.05 0.10.1 Detail A 0.50.2 1.0 0.10 0-10
Epoxy Cu Solder plate 1999/06 - 16 -
1 0.220.1
8 0.65
Seating Plane
NOTE: Dimension "*" does not include mold flash.
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment:
M0067-E-00
*4.4
ASAHI KASEI
[AK5353]
MARKING
AKM 5353VT XXYYY
1) 2)
3) 4)
Pin #1 indication Date Code : XXYYY (5 digits) XX: lot# YYY: Date Code Marketing Code : 5353VT Asahi Kasei Logo
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
M0067-E-00 - 17 -
1999/06

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